The application of the phase locked loop is quite broad. Upon FM (frequency modulation) demodulation, the phase locked loop can be used to lock the phase of the signal for improving the sound effect. It is notorious the performance of the phase locked loop depends on how the signal phase is locked about which the present invention contemplates to ascertain.
FIG. 1 shows a basic circuit for a phase locked loop (PLL) 1. On the one hand, the smaller the alignment difference between the input signal x and the output signal y is, the better the PLL performance will be. On the other hand, the smaller the jitter of the output signal y is or the stabler the output signal y is, the better the PLL performance will be.
As shown in FIGS. 2A & 2B, in the prior art, for obtaining the phase difference, a tester 2 set on a trigger mode with a trigger voltage adjusted on a specific level (normally one half of the high voltage, i.e. VDD/2) normally directly connects thereto input signal x and output signal y for obtaining time differences d1, d2, d3 . . . between times when pulses of input signal x and output signal y respectively reach said specific level, and then averages the absolute values of time differences d1, d2, d3 . . . to obtain the phase difference between input and output signals x, y.
It can be seen that input signal x and output signal y are connected to tester 2 through different paths. Ideally, two identical probes for tester 2 have the same equivalent impedance, and the contact impedances of the test clippers and the signal wires are also the same by which a good test result will be obtained, which, nevertheless, is impractical or impossible in the real world. For a signal in the megahertz or gigahertz frequency range, the included error in the tested result according to the prior art is unacceptable or is difficult to calculate.
As shown in FIG. 3, it has been the trend to use the PLL in a very large scale integration circuit (VLSI) 3. Since paths a, b of input signal x and output signal y in the chip are different and thus incurred equivalent impedances thereof will be different, the tested error will be significant if the conventional testing method is applied.
As shown in FIGS. 4A & 4B, for measuring the jitter, tester 2 with a trigger voltage set at one half of the high voltage finds that pulses of output signal y begin to rise at times t1, t2, t3 . . . After the time differences thereof d1, d2, d3 . . . are calculated, we can average them to obtain the averaged cycle Tc. The maximum of the differential values d1-Tc, d2-Tc, d3-Tc . . . between respectively averaged cycle Tc and time differences d1, d2, d3 . . . is the maximum jitter. On the contrary, the minimum of the differential values will be the minimum jitter.
It is therefore tried by the applicant to deal with the above situation encountered by the prior art and/or facilitate the test for the PLL.